The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a transistor element capable of performing 4-bit writing, and a semiconductor device equipped therewith and a manufacturing method thereof.
There has been known, for example, a semiconductor device that implements a ferroelectric memory cell capable of storing polarization data of a multivalue of three values or more in one ferroelectric film.
According to the configuration of the conventional semiconductor device, information equivalent to 4 bits in total are stored at positions of 4 points in total corresponding to two points of both ends as viewed in a first direction, of the ferroelectric element, and two points of both ends as viewed in a second direction orthogonal to the first direction (refer to a patent document 1 (Japanese Unexamined Patent Publication No. 2004-047593)).
With the objective of implementing a semiconductor device capable of performing a storage holding operation of 2 bits or more by one transistor and easy to make its scale-down, there has been known, for example, a configuration which includes a gate electrode and memory functional bodies formed on both sides of the gate electrode and having the function of holding electrons, and the amount of current flowing from one diffusion region to the other diffusion region at the application of a voltage to the gate electrode is changed depending on the size or magnitude of electrons held in the memory functional bodies (refer to a patent document 2 (Japanese Unexamined Patent Publication No. 2004-342927)).
An electrical characteristic of a conventional multi-valued transistor will now be explained with referent to FIG. 26.
FIG. 26 is a schematic graph showing cell current windows (memory windows) of the conventional multi-valued transistor. The vertical axis indicates a read current (Ids (Vt)) between the drain and source of the transistor, and the horizontal axis indicates the frequency.
A conventional transistor element capable of 4-bit writing/reading performs 2-bit writing/reading on one side of two side surfaces opposite to each other as viewed in the direction of a gate length of its gate electrode. Therefore, cell current windows (corresponding to intervals as viewed in the vertical axis) 100 between respective data (00, 01, 10 and 11) indicated by solid lines 110 were varied and narrowed as indicated by dotted lines 120 particularly when electrons existed in electron storage layers on the opposite sides of the gate electrode.
There is a fear that when the cell current windows are varied and narrowed as described above, the reading (determination) of the stored data from the transistor cannot be performed. As a result, there is the fear of a failure in transistor.